BlockBeats News, August 30th, Citrini analyst Jukan posted that, according to sources, the HBM specification used by NVIDIA's Rubin Ultra may be reduced from 12-layer HBM4E to 8 layers. Customers such as OpenAI and Anthropic even requested a 4-layer product but were rejected by the memory manufacturer. The current downspec may be limited to 8 layers. The main reason for the downspec is believed to be yield and cost pressure: if 12-layer HBM4E were used with price increases taken into account, the memory cost could account for approximately 70% of Rubin Ultra's overall material cost.

Software optimizations such as model quantization, MLA, and compute task partitioning are transferring low-frequency access KV caches and model states to LPDDR, CXL, and NAND, while HBM mainly retains the working set required for current computations. Therefore, after meeting the minimum capacity, customer emphasis on HBM bandwidth is beginning to outweigh capacity.

It is believed that reducing the stack layers can increase packaging yield, increase HBM and AI accelerator shipments, and may actually expand total HBM demand; higher bandwidth requirements will also reduce the proportion of chips in the wafer sorted by speed grades, further consuming DRAM wafer capacity. In the long term, HBM will eventually be replaced by new architectures, and the ultimate direction may be the fusion of storage and logic chips. The next two years will be a crucial stage to see if memory manufacturers can expand into the logic domain.