BlockBeats News, June 23. Analyst Damnang stated in an article published on June 22 that the newly released JEDEC SPHBM4 standard is not aimed at making DRAM itself faster, larger, or cheaper, but at changing the way HBM is connected to GPUs. Traditional HBM4 requires a GPU connection through a silicon interposer, while SPHBM4 attempts to bypass the silicon interposer and directly connect to an organic package substrate.

The technical core of SPHBM4 is to reuse the HBM4 DRAM stack, only redesigning the bottom base die. Traditional HBM4 has 2048 data signal pins and relies on a silicon interposer to handle the extremely tight pitch connections; SPHBM4 reduces the pin count to 512 and increases single-pin speed fourfold through 4:1 serialization, theoretically maintaining a bandwidth close to that of HBM4.

Damnang believes that the key to this standard is not in "cheap HBM" but in unlocking advanced packaging capacity. While HBM is expensive and in short supply, in AI accelerator shipments, the silicon interposer and CoWoS are also important bottlenecks. If HBM no longer occupies interposer area, the same interposer wafer capacity could potentially support more packaging shipments.

The article estimates that in high-end AI accelerators, HBM may occupy nearly half of the silicon interposer area. If this area is removed, the theoretically supported packaging quantity per wafer may increase by 1.5 to 2 times. However, the actual effect depends on adoption rates, yield, product configuration, and remaining GPU-side interposer area.

Therefore, SPHBM4 truly unlocks capacity rather than reducing the cost of a single chip. Even if similar technologies can save 22% to 40% of packaging costs, when applied to the total cost of an AI accelerator, it is only a single-digit percentage. More important than saving hundreds of dollars per chip is the potential increase in GPU and ASIC output after the shipment bottleneck is removed.

The beneficiaries may not be straightforward either. In the short term, even if a cloud provider or chip company is the first to adopt SPHBM4, the released CoWoS capacity may be reallocated by TSMC to waiting customers, with NVIDIA potentially being the best positioned to absorb the additional capacity. For cloud providers developing ASICs, the value of SPHBM4 may be more long-term: reducing reliance on large-area silicon interposers, enhancing design and shipment flexibility.

The industry chain value will also shift accordingly. Damnang stated that SPHBM4 will shift the technological burden from the substrate and silicon interposer to the high-speed logic design of the base die. With the increased single-pin speed, PHY, SerDes, clock recovery, equalization, and error correction circuits will become more critical. The focus of HBM competition may shift from "who can stack higher" to "who can optimize the underlying logic better".

At the company level, Samsung has a vertical integration advantage due to its capabilities in storage, advanced logic process, and packaging. SK Hynix and Micron rely more on TSMC's advanced nodes to achieve complex base dies. TSMC, even facing mid-tier area reduction, still holds the CoWoS and base die foundry. Intel, with EMIB, high-speed interconnect, and advanced packaging capabilities, emerges as a potential variable.

However, SPHBM4 is currently in the "standard release, awaiting adoption" stage. The next steps will require monitoring three things: which storage factory will be the first to launch SPHBM4 products, whether major cloud providers will incorporate this design into their in-house ASICs, and whether JEDEC will publicly disclose the complete technical details.

Damnang is an analyst who has long been focused on semiconductors and AI infrastructure. Their Substack mainly covers semiconductor, memory, advanced packaging, foundry, and AI chip industry chain analysis, with a focus on breaking down complex engineering issues into industry logic that investors can understand.