BlockBeats News, July 5th, Intel is considering adopting a dual side power delivery architecture in the 1.4nm ultrafine process, utilizing power from both the front and back to catch up with its competitors. According to industry sources, Intel originally planned to use the backside power delivery technology PowerDirect in the 1.4nm base process 14A, but in the subsequent 14A2 process, it is considering introducing a Dual side architecture that utilizes power from both the front and back simultaneously.

Intel previously announced its plan to achieve a 1.3x increase in chip density on the 14A process compared to 18A; the target M0 spacing on the 14A process is around 28nm, while the 14A2 process may advance the M0 spacing to 21nm through a half-node improvement. While maintaining the backside power delivery network as the main focus, Intel will redistribute some of the front-side metal wiring for auxiliary power and Clock signal purposes to compensate for the power margin deficiency caused by miniaturization and exposure limitations.

Intel's 14A process is scheduled to enter risk production in 2028 and mass production in 2029. Intel needs to release the 14A process 0.9 version process design kit to external customers in October this year and secure orders from major fabless clients within the following 18 months. In comparison, TSMC has planned to ship its true 1.4nm A14 products in 2028, while Samsung Electronics also plans to adopt a backside power delivery technology in its 2nm enhanced SF2Z process for commercial use in 2027.